A flat screen, especially a liquid-crystal flat screen, is made up of a number of electro-optical cells arranged in rows and columns, each controlled by a switching device and containing two electrodes bordering a liquid crystal whose optical properties are modified as a function of the value of the field traversing it. The assembly consisting of the switching device, the electrode, the liquid crystal, the counterelectrode constitutes what is termed a "pixel" or image point. The addressing of these pixels is performed by way of selection lines which control the on and off state of the switching devices and of columns or lines of data which transmit, when the switching device is on, a voltage applied to the terminals of the electrodes corresponding to the data signal to be displayed, namely to a grey scale.
According to a particularly advantageous embodiment, the electrodes, the switching devices, the lines and the columns are deposited and etched on the same substrate board in such a way as to constitute the active matrix of the screen. In this case, the peripheral control circuits, that is to say the selection line scanner which selects the horizontal lines to be displayed and the circuits which control the columns can be integrated directly onto the substrate board containing the active matrix and can be manufactured at the same time as the latter. These therefore make it necessary, especially when the number of pixels is very high, to have the smallest and simplest possible control circuits so as to achieve a high degree of manufacturing efficiency. It may moreover be advantageous to use semiconductor devices as pixel switching devices with the same conductivity type throughout the display.
Control of the semiconductor devices can be undertaken by lines addressed by one or more shift registers. A shift register structure which makes it possible in particular to meet the simplicity requirements alluded to in the previous paragraph has been described in International Patent Application WO 92/15992 filed in the name of THOMSON-LCD. In this case, a stage of a shift register contains six transistors and is fed with two clock signals and also from two positive sources and one negative source. The operation of this register relies on the fact that the gate of the transistor which controls the output of the stage of the register is left floating and that its potential therefore follows the potential of the clock and of the output, through a capacitive effect. This effect is termed the "bootstrap" effect. It allows, at the desired moment, complete charging of the output to the highest potential of the clock. With this output transistor are associated a transistor allowing the gate of the output transistor to be precharged and a transistor allowing it to be discharged. On the other hand, the operation of these three transistors is such that although the "bootstrap" effect allows proper charging of the outputs, it is accompanied by stray effects which make it necessary to use three supplementary transistors. Another drawback resides in the fact that certain transistors undergo permanent gate stress, namely a positive voltage on the gate, a consequence of which may be the drifting of their threshold voltage and may give rise in due course to a malfunction of the entire device.
To remedy the aforesaid drawbacks, French Patent Application No. 94 05987 filed on May 17, 1994 in the name of THOMSON-LCD proposes simpler circuits with three or four transistors having prolonged lifetimes.
Thus, as represented in FIG. 1 which corresponds to FIG. 2 of French Patent Application No. 94 05987, a stage 21 of a shift register making it possible to control the selection lines is made up of three transistors Tl, Tp and Td. In this case, the transistor Tl controls the node D of the output on the line J. It is precharged by the transistor Tp and discharged by the transistor Td. More precisely, the stage 21 is connected at 22 to the preceding line J-1 via the drain of the transistor Tp. The gate of the transistor Tp is connected to its drain whereas its source is connected to the point G, itself connected to the gate of the transistor Tl. On the other hand, the point G is linked to a negative voltage V- by way of the discharge transistor Td, itself controlled by the potential of the line J+1 connected at the output of the next stage. Moreover, the node D is connected to the source of the transistor Tl, to the node G by way of a capacitance Cb and to the line J to be selected whose charging is symbolized electrically by a capacitance Cl linked to earth 32. A clock signal .phi.1 is applied to the drain of the output transistor Tl. Between the drain and the gate of this transistor there is a stray capacitance Cp responsible for the "bootstrap" effect explained with reference to the Application WO 92/15992. Moreover in this layout, a clock .phi.2 exactly complementary to the clock .phi.1 is connected to the node G by way of a capacitance C2 of a value equivalent to that of the stray capacitance Cp.
Thus the stray effects, the consequence of the "bootstrap" effect, are counter-balanced by virtue of the linking of the clock .phi.2 (complementary to the clock .phi.1) with the gate of the transistor Tp by way of the capacitance C2 of value Ct equivalent to that of Cp. The two clocks being exactly complementary, they induce no stray voltage at the node G, namely on the gate of the transistor Tl. An equivalent circuit contains a capacitance Cl=2.times.Ct between the node G and earth 32. Such a structure reducing the "bootstrap" effect, it is necessary to add a "bootstrap" capacitance Cb between the source node D and the gate node G so that the voltage of the gate follows a fraction Cb/(Cb+2.times.Cp) of the variations in the source voltage. Thus, it suffices, in order that a "bootstrap" ratio of 60% be attained, that Cb have three times the value of Ct. The circuit described above preserves the "bootstrap" effect without its secondary effects. The lifetime of the circuit and hence of the entire device is prolonged while the number of transistors required is halved as compared with the prior art.
The operation of the circuit is explained with reference to the timing diagrams 2a to 2f each of them showing a timescale as abscissa and a potential as ordinate. When the preceding stage J-1 sends a pulse (FIG. 2c) in 22, the precharge transistor Tp is on and charges the "bootstrap" capacitance Cb. The potential of the node G (FIG. 2d) rises to that of the line J-1 corresponding to the preceding stage, from which must be deducted substantially the value of the threshold voltage of the transistor Tp. The transistor Tl is then on. When the clock .phi.1 rises in turn (FIG. 2a) the output J follows, carrying with it the gate of the transistor Tl by virtue of the "bootstrap" capacitance (FIG. 2d) . The transistor Tl is then fully on and the node D and the line J follow the potential of the clock .phi.1 perfectly (FIG. 2e) until it falls. At this moment, the next line J+1 rises (FIG. 2f) and turns on the transistor Td which discharges the "bootstrap" capacitance Cb so that the transistor Tl is no longer on for the succeeding clock beats (FIG. 2d).
The circuit described with reference to FIG. 1 has been enhanced in French Patent Application No. 94 05987 by adding a transistor which makes it possible to work with control signals having an amplitude of 5 to 10 volts less than that of the output signals. This solution is represented in FIG. 3. This figure depicts three transistors MN2, MN1 and MN3 which are equivalent to the transistors Tl, Tp and Td, the two inputs n-1 and n+1 equivalent to J-1 and J+1, the two clock inputs .phi.1 and .phi.2 in phase opposition, the output n of the stage equivalent to the output J as well as the capacitances C1, C2 CR corresponding respectively to the capacitances C2, Cb, Cl of the embodiment described with reference to FIG. 1. In this case there is provided a reset-to-zero transistor MN4 which connects the node D to a negative voltage Vgoff. The gate of the transistor MN4 is connected to the node Z, itself linked to the output of the next stage n+1 or to the line n+2, that is to say to the output line of the next but one stage. As described in the French Application, such a structure allows resetting to zero with a simplified circuit. Moreover, provided between the output line n and a voltage Vcomp is a compensation capacitance C comp.